1. Field of the Invention
This invention relates to integrated circuit fabrication and, more particularly, to a method for simultaneously forming lightly doped drain areas and source/drain areas for high-performance transistors.
2. Description of the Related Art
Because of the increased desire to build faster and more complex integrated circuits, it has become necessary to reduce the transistor threshold voltage, V.sub.T. Several factors contribute to V.sub.T, one of which is the effective channel length ("L.sub.eff ") of the transistor. The initial distance between the source-side junction and the drain-side junction of a transistor is often referred to as the physical channel length, L. However, after implantation and subsequent diffusion of the junctions, the actual distance between junctions becomes less than the physical channel length and is often referred to as the effective channel length. In VLSI designs, as the physical channel length decreases, so too must L.sub.eff. Decreasing L.sub.eff reduces the distance between the depletion regions associated with the source and drain of a transistor. As a result, less gate charge is required to invert the channel of a transistor having a short L.sub.eff. Accordingly, reducing L, and hence L.sub.eff, can lead to a reduction in the threshold voltage of a transistor. Consequently, the switching speed of the logic gates of an integrated circuit employing transistors with reduced L.sub.eff is faster, allowing the integrated circuit to quickly transition between logic states (i.e., operate at high frequencies). Minimizing L also improves the speed of integrated circuits including a large number of individual transistors because the larger drain current associated with a short channel length can drive the adjoining transistors into saturation more quickly. Minimizing L is, therefore, desirable from a device operation standpoint.
In addition, minimizing L is desirable from a manufacturing perspective because a smaller area of silicon is required to manufacture a transistor having a smaller length. By minimizing the area required for a given transistor, the number of transistors available for a given area of silicon increases, with a corresponding increase in the circuit complexity that can be achieved on the given area of silicon. As layout densities increase, however, the problems associated with fabrication of transistors are exacerbated. N-channel devices are particularly sensitive to so-called short-channel effects ("SCE"). SCE become a predominant problem whenever L.sub.eff drops below approximately 1.0 .mu.m.
A problem related to SCE and the subthreshold currents associated therewith is the problem of hot-carrier effects ("HCE"). HCE are phenomena by which the kinetic energy of the carriers (holes or electrons) is increased as they are accelerated through large potential gradients and subsequently become trapped within the gate dielectric. The greatest potential gradient, often referred to as the maximum electric field ("E.sub.m "), occurs near the drain during saturated operation. More specifically, the electric field is predominant at the lateral junction of the drain adjacent the channel. The electric field at the drain primarily causes electrons in the channel to gain kinetic energy and become "hot." As hot electrons travel to the drain, they lose their energy by a process called impact ionization. Impact ionization serves to generate electron-hole pairs, wherein the pairs migrate to and become injected within the gate dielectric near the drain junction. Traps within the gate dielectric generally become electron traps, even if they are partially filled with holes. As a result, there is a net negative charge density in the gate dielectric. The trapped charge accumulates with time, resulting in a positive threshold shift in the NMOS transistor, or a negative threshold shift in a PMOS transistor.
To overcome the problems of sub-threshold current and threshold shift resulting from SCE and HCE, an alternative drain structure known as lightly doped drain ("LDD") is commonly used. The purpose of the LDD is to absorb some of the potential into the drain and thus reduce E.sub.m. LDD areas and source/drain areas are conventionally formed sequentially. LDD areas are typically formed self-aligned to sidewall surfaces of the gate conductor by implanting a light concentration of dopant ions into the semiconductor substrate. The light implant dose serves to produce a lightly doped section within the junction at the gate edge near the channel. Spacers are then formed adjacent the sidewalls of the gate conductor and a second implant of dopant species forwarded into the semiconductor substrate to form source/drain areas a lateral spaced distance from the gate conductor. The second implant is performed at a higher concentration than the first implant. The second implant is also performed at a higher energy than the first implant, so that the peak concentration of the source/drain areas resides at a depth greater than the peak concentration of the lightly doped drain areas. As a result, a dopant gradient (i.e., "graded junction") occurs at the interface between the source and channel as well as between the drain and channel.
Associated with the conventional method of lightly doped drain and source/drain formation, however, are several disadvantages. With two impurity implants separated by a spacer formation step, the fabrication process is complicated and time-consuming. The multiplicity of steps also allows increased opportunity for introduction of unwanted contaminants into the device being fabricated during transfer between processes. Further, the size of the spacers formed according to the conventional method is fairly fixed. Thus, as the channel length of transistors is decreased, the lateral dimension of the spacers, and thus of the lightly doped drain areas masked by them, increases as a proportion of the channel length. Unfortunately, the addition of an LDD implant adjacent the channel adds capacitance and resistance to the source/drain pathway. This added resistance, generally known as parasitic resistance, can have many deleterious effects. First, parasitic resistance can decrease the saturation current (i.e., current above threshold). Second, parasitic capacitance can decrease the overall speed of the transistor.
It would therefore be desirable to derive a method for fabricating a transistor in which the need for sidewall spacers is eliminated. Eliminating the need for spacers may facilitate fabrication of sub-micron gate conductors as well as allow increased control of lightly doped drain dimensions, thus minimizing parasitic resistance in transistors having small lateral dimensions. In addition, deriving a method for fabricating lightly doped drain areas simultaneously with source/drain areas would be desirable, in that such a method may simplify the manufacturing process and improve device quality.